Fakultät für Informatik
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Technische Universität München
Lehrstuhl für Effiziente Algorithmen
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Experiments on optimizing the performance of stencil codes with SPL conqueror
Alexander Grebhahn
,
Sebastian Kuckuk
,
Christian Schmitt
,
Harald Köstler
,
Norbert Siegmund
,
Sven Apel
,
Frank Hannig
,
Jürgen Teich
Parallel Processing Letters
24
(3), 2014, pp. 19 pages
Towards a performance-portable description of geometric multigrid algorithms using a domain-specific language
Richard Membarth
,
Oliver Reiche
,
Christian Schmitt
,
Frank Hannig
,
Jürgen Teich
,
Markus Stürmer
,
Harald Köstler
Journal Parallel Distributed Computing
74
(12), 2014, pp. 3191-3201
Acceleration of optical flow computations on tightly-coupled processor arrays
Éricles Rodrigues Sousa
,
Alexandru Tanase
,
Vahid Lari
,
Frank Hannig
,
Jürgen Teich
,
Johny Paul
,
Walter Stechele
,
Manfred Kröhnert
,
Tamin Asfour
Mitteilungen - Gesellschaft für Informatik e.V., Parallel-Algorithmen und Rechnerstrukturen
(30), 2013, pp. 80-89
Self-organizing core allocation
Tobias Ziermann
,
Stefan Wildermann
,
Jürgen Teich
Mitteilungen - Gesellschaft für Informatik e.V., Parallel-Algorithmen und Rechnerstrukturen
(30), 2013, pp. 90-101
Mapping of nested loop programs onto massively parallel processor arrays with memory and I/O constraints
Hritam Dutta
,
Frank Hannig
,
Jürgen Teich
HNI-Verlagsschriftenreihe
181
, 2006, pp. 97-119
Higher-dimensional packing with order constraints
Sándor P. Fekete
,
Ekkehard Köhler
,
Jürgen Teich
SIAM Journal on Discrete Mathematics
20
(4), 2006, pp. 1056-1078
Energy estimation of nested loop programs
Frank Hannig
,
Jürgen Teich
Proceedings of the 14th Annual ACM Symposium on Parallel Algorithms and Architectures, SPAA'2002 (Winnipeg, Canada, August 10-13, 2002)
, 2002, pp. 149-150
Higher-dimensional packing with order constraints
Sándor P. Fekete
,
Ekkehard Köhler
,
Jürgen Teich
Lecture Notes in Computer Science
2125
, 2001, pp. 300-312
Optimization of dynamic hardware reconfigurations
Jürgen Teich
,
Sándor P. Fekete
,
Jörg Schepers
misc, 2000, August
Partitioning processor arrays under resource constraints
Jürgen Teich
,
Lothar Thiele
,
Lee Z. Zhang
Journal of VLSI Signal Processing
17
, 1997, pp. 5-20
Minimal communication in massive parallel architectures
Jürgen Teich
,
Li Zhang
,
Lothar Thiele
Mitteilungen - Gesellschaft für Informatik e.V., Parallel-Algorithmen und Rechnerstrukturen
(12), 1993, pp. 154-161