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High level simulation of SVP many-core systems
M. Irfan Uddin
,
Michiel W. van Tol
,
Chris R. Jesshope
Parallel Processing Letters
21
(4), 2011, pp. 413-438
On the compilation of a language for general concurrent target architectures
Thomas A.M. Bernard
,
Clemens Grelck
,
Chris R. Jesshope
Parallel Processing Letters
20
(1), 2010, pp. 51-69
Operating systems in silicon and the dynamic management of resources in many-core chips
Chris Jesshope
Parallel Processing Letters
18
(2), 2008, pp. 257-274
Microthreading a model for distributed instruction-level concurrency
Chris Jesshope
Parallel Processing Letters
16
(2), 2006, pp. 209-228
Latency reduction in VLSI routers
Chris Jesshope
Parallel Processing Letters
3
(4), 1993, pp. 485-494
Transputers and switches as objects in OCCAM
Chris Jesshope
Parallel Computing
8
(1-3), 1988, pp. 19-30
Implementations of load balanced active-data models of parallel computation
Chris Jesshope
misc, 1987